1. Field of the Invention
The present invention relates to simplification of a manufacturing process for complementary semiconductor devices, which are becoming increasingly miniaturized and increasingly complex, to a high component-density semiconductor device having enhanced resistance to CMOS latch-up, and to well formation (single, twin, triple).
2. Description of the Related Art
The importance of CMOS technology in the VSLI field has grown, as a result of requirements for a high noise margin and low power consumption. However, as miniaturization has increased, serious problems have arisen with regard to preventing stray thyristor operation which causes the CMOS latch-up phenomenon to occur between mutually adjacent portions of an n-channel MOSFET and p-channel MOSFET, and with regard to maintaining a sufficient level of withstanding voltage between mutually adjacent elements.
Various forms of device configuration and manufacturing process have been proposed for overcoming these problems. These proposals include the use of a configuration containing wells, formation of a buried high concentration layer, and formation of a self-aligned channel stop at the edge of a well region.
Summaries of these various structures and methods have been presented, for example, in U.S. Pat. No. 5,160,996 at column 1 line 34 et seq. Additional disclosure of this technology appears in the article entitled "MeV implantation technology: Next-generation manufacturing with current-generation equipment" by Borland and Koelsch in the December 1993 issue of Solid State Technology.